tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 58

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

●CP0 register
● Interrupt controller
Exceptions/Interrupts
Cause
Status
VAddr
SSCR
Error
ILEV
EPC
EPC
Bad
detected and the IVR register setting of the interrupt controller is changed when maskable interrupt is detected.
These changes are described in “6.2 Reset exception/ non-maskable interrupt” and “6.5 Hardware interrupt”.
“-“ indicates no change. Factors shown with （） are changed by specific exceptions.
Other than the registers shown above, the NMIFLG register setting changes when non-maskable interrupt is
This table excludes the changes related to debug exceptions. See “TX19A/H1 architecture” for these changes.
CMASK
ExcCod
PMASK
CE[1:0]
CSS
BEV
ERL
PSS
NMI
EXL
RP
BD
e
-
-
-
Reg
Set
PC
No
0
1
0
1
-
-
-
-
-
-
-
-
-
Reg
Set
PC
No
-
-
1
1
-
-
-
-
-
-
-
-
-
Factor
Code
(Addr)
(Cop
Reg
No)
Set
1/0
PC
-
No
-
1
-
-
-
-
-
-
Table 6.3 Register filed change
TMP19A44(rev1.3) 6-8
Level
Level
Cod
Reg
Reg
Set
Set
1/0
PC
No
No
1
e
-
-
-
-
-
-
-
Low-power consumption mode is set （ select Halt/Doze） .
Exception handler address has been changed.
NMI is generated.
Reset/ NMI is generated.
Interrupt prohibited when this bit is set.
Exception (other than reset/NMI) is generated.
Interrupt prohibited when this bit is set.
1: exception/ interrupt is generated in the slot of branch
0: others
（This bit changes only when the EXL bit of the status
register is “0”.）
Co-processor number referred when co-processor
unusable exception is generated.
Code according to exception/ interrupt.
Program counter of an instruction executed when a
It indicates program counter of branch instruction when a
Virtual address considered to be an error when an
address error exception is generated.
Register set number.
When the SSD bit of the SSCR register （bit to enable the
CSS contents set before an interrupt is stored in PSS.
CMASK: detected interrupt level
PMASK: CMASK value before interrupt generation
factor is detected.
shadow register）is “0” (enabled), an interrupt changes
the
corresponding to the detected interrupt level. (the
shadow register switching)
instruction.
factor is detected in the branch instruction slot.
CSS
bit
to
Meaning
select
The
TMP19A44
shadow
2010-04-01
register