tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 253

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

External Bus Interface
(3) Release of bus control authority
Internal address
The TMP19A44 recognizes that the BUSRQ is at the "L" level, and releases the bus at the end of the bus
cycle.
When the bus is completed, the TMP19A44 asserts BUSAK . The external bus master recognizes that the
The external bus master releases the bus control authority when it becomes unnecessary.
If the external bus master no longer needs the bus control authority that it has held, it negates the BUSRQ
signal and returns the bus control authority to the TMP19A44.
Fig. 8.20 shows the timing of releasing unnecessary bus control authority.
The external bus master has the bus control authority.
The external bus master deasserts the BUSRQ , as it no longer requires the bus control authority.
The TMP19A44 recognizes that the BUSRQ is at the "H" level, and deasserts the BUSAK .
External address
External address
BU SRQ
BU SAK
BUSRQ is at the "H" level.
BUSAK is at the "L" level, and acquires the bus control authority to start bus operations.
Internal address
BUSRQ
BUSAK
TMP19A4 4 external access
TMP19A4 4 external access
Fig. 8.20 Timing of Releasing Bus Control Authority
Fig. 8.19 Bus Control Authority Acquisition Timing
TMP19A44 external access
TMP19A44 exter nal access
TMP19A44 (rev1.3) 8-25
tsys
External bus mas ter cy cle
External bus master cycle
tsys
TMP19A44 ext ernal ac ces s
TMP19A44 external access
TMP19A44 external access
TMP19A44 exter na l access
TMP19A44
2010-04-01