tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 70

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.4.2 Software Interrupt Handling
6.4.2.1
CPU handles interrupt
CPU detects interrupt
CPU branches off to
exception handler
The following shows how a software interrupt is handled.
Interrupt factor is
Processing
generated
Flowchart
indicates hardware handling.
TMP19A44(rev1.3) 6-20
Set the following bits in the CP0 register.
Status<IM>[1:0]
Cause<IP>[1:0]
Status<IE>
The CPU detects the interrupt.
The CPU handles the interrupt.
The following bits in the CP0 register are automatically set.
The CPU branches off to the exception vector address.
An interrupt vector address differs depending on combination of the
BEV bit in the Status register and the IV bit in the Cause register.
Detection is unavailable in the following conditions.
-Status<ERL> or Status<EXL> bit is set
-In debug mode
-The CPU is stalled.
At least 3 clocks are required to detect the interrupt after the factor
is generated.
CP0:
CP0:
CP0:
IV=0
IV=1
Status[EXL]
ErrorEPC
Cause[BD]
indicates software handling.
0x8000_0180
0x8000_0200
BEV=0
Details
←
←
←
0xBFC0_0380
0xBFC0_0400
“1”
“PC of exception”(Note)
“1/0”(Note)
BEV=1
TMP19A44
2010-04-01