tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 277

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DMA Controller (DMAC)
SARn
10.3.5
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
31 : 0
Bit
Source Address Registers (SARn)
Mnemonic
SAddr
SAddr15
SAddr23
SAddr31
SAddr7
23
31
15
7
Fig. 10.7 Source Address Register (SARn)
Source address
SAddr22
SAddr30
SAddr14
SAddr6
TMP19A44 (rev1.3) 10-14
Field name
14
22
30
6
SAddr13
SAddr21
SAddr29
SAddr5
13
21
29
5
Source Address (initial value: −)
Specifies the address of the source from which data is
transferred using a physical address. This address changes
according to the SAC and TrSiz settings of CCRn and the
SACM setting of DTCRn.
See detailed description.
See detailed description.
See detailed description.
See detailed description.
SAddr12
SAddr20
SAddr28
SAddr4
12
20
28
Indeterminate
Indeterminate
Indeterminate
Indeterminate
4
R/W
R/W
R/W
R/W
SAddr11
SAddr19
SAddr27
SAddr3
11
19
27
3
Description
SAddr10
SAddr18
SAddr26
SAddr2
10
18
26
2
TMP19A44
SAddr17
SAddr25
SAddr1
SAddr9
17
25
1
9
2010-04-01
SAddr16
SAddr24
SAddr0
SAddr8
16
24
0
8