tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 254

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

9.
The Chip Selector and Wait Controller TMP19A44 (rev1.3) 9-1
9.1 Specifying Address Spaces
The Chip Selector and Wait Controller
The TMP19A44 can be connected to external devices (I/O devices, ROM and SRAM).
4-block address spaces (CS0 through CS3) can be established in the TMP19A44 and three parameters can be
specified for each 4-block address and other address spaces: data bus width, the number of waits and the number
of dummy cycles.
CS3. These pins generate chip selector signals (for ROM and SRAM) to each space when the CPU designates
an address in which spaces CS0 through CS3 are selected. For chip selector signals to be generated, however,
the port 4 controller register (P4CR) and the port 4 function registers (P4FC1 and P4FC2) must be set
appropriately.
The specification of the spaces CS0 through CS3 is to be performed with a combination of base addresses (BAn,
n=0 to 3) and mask addresses (MAn, n=0 to 3) using the base and mask address setting registers (BMA0 through
BMA3).
Meanwhile, master enable, data bus width, the number of waits and the number of dummy cycles for each
address space are specified in the chip selector and wait controller registers (B01CS, B23CS).
A bus wait request pin ( WAIT /RDY) is provided as an input pin to control the status of these settings.
Spaces CS0 through CS3 are specified using the base and mask address setting registers (BMA0 through
BMA3).
In each bus cycle, a comparison is made to see if each address on the bus is located in the space CS0 through
CS3. If the result of a comparison is a match, it is considered that the designated CS space has been accessed
and chip selector signals are output from pins CS0 through CS3 and the operations specified by the chip
selector and wait controller registers (B01CS and B23CS) are executed. (Refer to "9.2 The Chip Selector and
Wait Controller.")
CS0 through CS3 (also used as P40 through P43) are the output pins corresponding to spaces CS0 through
9.1.1 Base and Mask Address Setting Registers
Fig. 9.1 show base and mask address setting registers. For base addresses (BA0 through BA3), a start
address in the space CS0 through CS3 is specified. In each bus cycle, the chip selector and wait
controller compare values in their registers with addresses and those addresses with address bits masked
by the mask address (MA0 through MA3) are not compared. The size of an address space is determined
by the mask address setting.
(1) Base addresses
Base address BAn specifies the higher-order 16 bits (A31 through A16) of the start address. The lower-
order 16 bits (A15 to A0) of the start address are always set to "0." Therefore, the start address begins
with 0x0000_0000H and increases in 64 kilobyte units.
shows the relationship between the start address and the BAn value.
(2) Mask addresses
Mask address (MAn) specifies which address bit value is to be compared. The address on the bus that
corresponds to the bit for which "0" is written on the address mask MAn is to be included in address
comparison to determine if the address is in the area of the CS0 to CS3 spaces. The bit for which "1" is
written is not included in address comparison.
CS0 to CS3 spaces have different address bits that can be masked by MA0 to MA3.
(Note 1) Address settings must be made using physical addresses.
(Note 2) CS areas must not be set in the internal area (
CS0 space and CS1 space: A29 through A14
CS2 space and CS3 space: A30 through A15
0xFF00_0000~0xFFFF_FFFF
TMP19A44
).
2010-04-01