tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 114

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
Be sure to set active state of the clear request if interrupt is enabled for clearing the STOP/ IDLE /
SLEEP standby modes.
(Note 1) When using interrupts, be sure to follow the sequence of actions shown below:
(Note 2) Settings must be performed while interrupts are disabled.
(Note 3) For clearing the STOP modes with TMP19A44, 32 interrupt factors (INT0 through INTB，
(Note 4) Among the above 12 factors to be assigned as the STOP/IDLE mode clear request interrupts,
INT10 through INT1B, PHCNT0 through PHCNT5 and KWUP) are available. You can use CG
for selecting edge/level of active state and judging whether the aforementioned factors are to
be used for clearing the STOP/ SLEEP/ IDLE modes.
INT0 to INTF and INT10 to INT1F can be used as a normal interrupt without setting CG. Select
level or edge with INTC. Setting CG is required when using an interrupt of both edges. The
interrupt factors excluding other than the assigned as the STOP/ IDLE clear request factors
need to be set to the INTC block.
1) If shared with other general ports, enable the target interrupt input.
2) Set conditions such as active state upon initialization.
3) Clear interrupt requests.
4) Enable interrupts.
TMP19A44(rev1.3) 6-64
TMP19A44
2010-04-01