tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 407

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Direction of Data Transfer
Stop Bit Length
Status Flag
Configurations of Send/Receive Buffers
software reset
Serial Channel (HSIO)
In the I/O interface mode, the direction of data transfer can be switched between "MSB first" and "LSB
first" by the data transfer direction setting bit <DRCHG> of the HC0MOD2 serial mode control register
2. Don't switch the direction when data is being transferred.
In the UART mode transmission, the stop bit length can be set to either 1 or 2 bits by bit 4 <SBLEN> of
the HC0MOD2 register.
If the double buffer function is enabled (HC0MOD2 <WBUF> = "1"), the bit 6 flag <RBFLL> of the
HC0MOD2 register indicates the condition of receive buffer full. When one frame of data has been
received and transferred from buffer 1 to buffer 2, this bit is set to "1" to show that buffer 2 is full (data
is stored in buffer 2). When the receive buffer is read by CPU/DMAC, it is cleared to "0." If <WBUF>
is set to "0," this bit is insignificant and must not be used as a status flag. When double buffering is
enabled (HC0MOD2 <WBUF> = "1"), the bit 7 flag <TBEMP> of the HC0MOD2 register indicates
that send buffer 2 is empty. When data is moved from send buffer 2 to send buffer 1 (shift register), this
bit is set to "1" indicating that send buffer 2 is now empty. When data is set to the send buffer by
CPU/DMAC, the bit is cleared to "0." If <WBUF> is set to "0," this bit is insignificant and must not be
used as a status flag.
3.
(HSCLK output)
(HSCLK input)
Framing error <FERR>: Bit 2 of the HC0CR register
In the UART mode, this bit is set to "1" when a framing error is generated. This flag is set to
"0" when it is read. A framing error is generated if the corresponding stop bit is determined to
be "0" by sampling the bit at around the center. Regardless of the <SBLEN> (stop bit length)
setting of the serial mode control register 2, HC0MOD2, the stop bit status is determined by
only 1 bit on the receive side.
I/O interface
I/O interface
Operation mode
UART
I/O interface
(HSCLK input)
I/O interface
(HSCLK output)
UART
TMP19A44(rev1.3) 15-17
Transmit buffer
Transmit buffer
Transmit buffer
Receive buffer
Receive buffer
Receive buffer
Error flag
OERR
PERR
FERR
OERR
PERR
FERR
OERR
PERR
FERR
<WBUF> = 0
Function
Overrun error flag
Parity error flag
Framing error flag
Overrun error flag
Underrun error flag (WBUF = 1)
Fixed to 0 (WBUF = 0)
Fixed to 0
Operation undefined
Operation undefined
Fixed to 0
Double
Double
Single
Single
Single
Single
<WBUF> = 1
Double
Double
Double
Double
Double
Double
TMP19A44
2010-04-01