tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 106

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
IMCGA
6.6.3.1
6.6.3 Clock Generator Register
INTCG register (STOP/SLEEP/IDLE clear interrupt)
(Note 1)
(Note 2)
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
“0” is read. Active state setting of INT0 standby
“0” is read. Active state setting of INT1 standby
“0” is read. Active state setting of INT2 standby
“0” is read. Active state setting of INT3 standby
Refer to EMSTxx bit to know the active condition which is used for clearing
standby.
Please specify the bit for the edge first and then specify the bit for the
<INTxEN>. Setting them simultaneously is prohibited.
15
23
31
7
R
R
R
R
0
0
0
0
clear request. (101~111: setting
prohibited)
clear request. (101~111: setting
prohibited)
clear request. (101~111: setting
prohibited)
clear request. (101~111: setting
prohibited)
EMCG22
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
EMCG0
EMCG1
EMCG3
14
22
30
6
2
2
2
0
0
0
0
TMP19A44(rev1.3) 6-56
EMCG0
EMCG1
EMCG2
EMCG3
R/W
R/W
R/W
R/W
13
21
29
5
1
1
1
1
1
1
1
1
EMCG0
EMCG1
EMCG2
EMCG3
12
20
28
4
0
0
0
0
0
0
0
0
standby clear request
standby clear request
standby clear request
standby clear request
Active state of INT0
Active state of INT1
Active state of INT2
Active state of INT3
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
EMST0
EMST1
EMST2
EMST3
19
27
11
3
1
0
1
0
1
0
1
0
R
R
R
R
EMST0
EMST1
EMST2
EMST3
10
18
26
2
0
0
0
0
0
0
0
0
TMP19A44
“0” is read. INT0 clear
“0” is read. INT1 clear
“0” is read. INT2 clear
“0” is read. INT3 clear
17
25
1
R
9
R
R
R
0
0
0
0
2010-04-01
input
0: Disable
1: Enable
input
0: Disable
input
0: Disable
1: Enable
input
0: Disable
1: Enable
1: Enable
INT0EN
INT1EN
INT2EN
INT3EN
R/W
R/W
R/W
R/W
16
24
0
8
0
0
0
0