tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 455

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Bus Interface (SBI)
16.7.2
The transmit mode, the receive mode or the transmit/receive mode can be selected by programming
SBICR1 <SIOM1:0>.
8-bit transmit mode
Set the control register to the transmit mode and write the transmit data to SBIDBR.
After writing the transmit data, writing "1" to SBICR1 <SIOS> starts the transmission. The
transmit data is moved from SBIDBR to a shift register and output to the SO pin, with the least-
significant bit (LSB) first, in synchronization with the serial clock. Once the transmit data is
transferred to the shift register, SBIDBR becomes empty, and the INTS0 (buffer-empty) interrupt is
generated, requesting the next transmit data.
In the internal clock mode, the serial clock will be stopped and automatically enter the wait state, if
next data is not loaded after the 8-bit data has been fully transmitted. The wait state will be cleared
when SBIDBR is loaded with the next transmit data.
In the external clock mode, SBIDBR must be loaded with data before the next data shift operation
is started. Therefore, the data transfer rate varies depending on the maximum latency between
when the interrupt request is generated and when SBIDBR is loaded with data in the interrupt
service program.
At the beginning of transmission, the same value as in the last bit of the previously transmitted data
is output in a period from setting SBISR <SIOF> to "1" to the falling edge of SCK.
Transmission can be terminated by clearing <SIOS> to "0" or setting <SIOINH> to "1" in the
INTS0 interrupt service program.
transmission ends. The program checks SBI0SR <SIOF> to determine whether transmission has
come to an end. <SIOF> is cleared to "0" at the end of transmission. If <SIOINH> is set to "1,"
the transmission is aborted immediately and <SIOF> is cleared to "0."
In the external clock mode, <SIOS> must be set to "0" before the next transmit data shift operation
is started. Otherwise, operation will stop after dummy data is transmitted.
INTS0 interrupt
Transfer Modes
SBICR1
SBIDBR
SBICR1
SBIDBR
← 0 1 0 0 0 X X X
← X X X X X X X X
← 1 0 0 0 0 X X X
← X X X X X X X X
7 6 5 4 3 2 1 0
TMP19A44 (rev1.3) 16-31
If <SIOS> is cleared, remaining data is output before
Selects the transmit mode.
Writes the transmit data.
Starts transmission.
Writes the transmit data.
TMP19A44
2010-04-01