tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 26

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.
Processor Core
3.1
3.1.1 Initial state
3.1.2 Operation
3.1.3 Cancellation
Processor Core
The TMP19A44 has a high-performance 32-bit processor core (TX19A/H1 processor core). For information on the
operations of this processor core, please refer to the "TX19A/H1 Architecture."
This chapter describes the functions unique to the TMP19A44 that are not explained in that document.
The internal circuits, register settings and pin status of the TMP19A44 are undefined right after the power-on. The
state continues until the RESET pin receives low level input after all the power supply voltage is applied.
As the precondition, ensure that an internal high-frequency oscillator provides stable oscillation while power supply
voltage is in the operating range. To reset the TMP19A44, input RESET signal at low level “0” for a minimum
duration of 12 system clocks (1.2ms with external 10MHz oscillator).
When the reset is canceled, the system control coprocessor (CP0) and the internal I/O register of the TX19A/H1
processor core are initialized. Note that the clock gear enters 1/1 mode and the PLL multiplication circuit stops after
canceling the reset. Therefore, setting for the PLL operation is required.
After the reset exception handling is executed, the program branches off to the exception handler. The address to
which the program branches off to (address where exception handling starts) is called an exception vector address.
This exception vector address of a reset exception (for example, nonmaskable interrupt) is 0xBFC0_0000 (virtual
address).
The register of the internal I/O is initialized.
The port pin (including the pin that can also be used by the internal I/O) is set to a general-purpose input or output
port mode.
Reset Operation
(Note 1) Set the RESET pin to "0" before turning the power on. Perform the reset after the
(Note 2) After turning the power on, make sure that the power supply voltage and
(Note 3) In the FLASH program, the reset period of 0.5 uS or longer is required
(Note 4) The reset operation can alter the internal RAM state, but does not alter data in the
power supply voltage has stabilized sufficiently within the operating range.
oscillation have stabilized, wait for 500 μs or longer, and perform the reset.
independently of the system clock.
backup RAM except for backup RAM.
TMP19A44 (rev1.3) 3-1
TMP19A44
2010-04-01