tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 88

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.5.2.6
(1) Change in CP0 Register
(Note) CSS and PSS change only when SSD of the SSCR register is set to “1” (using shadow
CPU processing
exception handler.
register).
On detecting the interrupt, the CPU updates appropriate field in the CP0 register and branches off to the
Generating an interrupt changes the following values in the CP0 register.
●CP0 register
Status<EXL>
Cause<BD>
Cause<ExcCode>
EPC
SSCR<CSS>
SSCR<PSS>
←
←
←
←
←
←
TMP19A44(rev1.3) 6-38
“1” (Interrupt prohibited)
Exception/ interrupt occurs in a branch slot: “1”
Others: “0”
Code according to exception/ interrupt
Ex) Interrupt: “0y00000”
PC of the instruction being executed when interrupt is
generated.
Same value as the interrupt level (note)
Interrupt level value is set as the new register set number.
CSS value of the pre-interrupt (*)
Shadow register set number of the pre-interrupt
TMP19A44
2010-04-01