tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 80

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

standby mode
Not clearing
Exceptions/Interrupts
(factor to clear standby
CPU Handles interrupt
INTC detects interrupt
CPU detects interrupt
CG detects interrupt
CPU branches off to
exception handler
Processing
mode)
Clearing standby
mode
The interrupt, which is used for clearing the standby modes, is
connected to INTC via the clock generator.
INTC detects the interrupt according to the setting in the INTC
IMC register.
The CPU is notified of the interrupt factor with the highest
priority according to the priority order.
The CPU detects the interrupt.
The CPU handles the interrupt.
Update the field related to the CP0register. Switch a shadow
register set.
Output a signal to accept interrupt to INTC.
The CPU branches off to the exception vector address.
An interrupt vector address differs depending on combination
of the BEV bit in the Status register and the IV bit in the Cause
register.
Detection is unavailable in the following conditions.
-Status<ERL> or Status<EXL> bit is set
-In debug mode
-The CPU is stalled.
TMP19A44(rev1.3) 6-30
IV=0
IV=1
0x8000_0180
0x8000_0200
BEV=0
Details
0xBFC0_0380
0xBFC0_0400
BEV=1
TMP19A44
2010-04-01
processing
Detection
Detection
Detection
by INTC
by CPU
6.5.2.3
6.5.2.4
6.5.2.5
6.5.2.6
by CG
CPU
See