tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 575

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

JTAG Interface
23.3 JTAG Controller and Registers
The following JTAG controller and registers are built into the processor:
In the JTAG basic mechanism, the TAP controller state machine monitors the signals input through the JTMS
pin. As the JTAG mechanism starts operation, the TAP controller determines a test function to be executed by
loading data into the JTAG instruction register (IR) and performing a serial data scan via the data register (DR),
as shown in Table 23-1. When data is scanned, the state of the JTMS pin represents new specific data words and
the end of data flow. The data register is selected according to data loaded into the instruction register.
23.3.1
Most significant to least
MSB
•
•
•
•
•
The JTAG instruction register consists of four cells, including shift registers. It is used to select either a
test to be executed or a test data register to be accessed or to select both. Either the boundary scan
register or the bypass register is selected according to combinations shown in Table 23-1.
Fig. 23-3 shows the format of the instruction register.
Instruction code
significant bit
0010 to 1110
Instruction register
Boundary scan register
Bypass register
Device identification register
Test Access Port (TAP) controller
Instruction Register
0000
0001
1111
3
Table 23-1 Bit Configurations of the JTAG Instruction Register
Fig. 23-3 Instruction Register
SAMPLE/PRELOAD
TMP19A44(rev1.3) 23-3
Instruction
BYPASS
EXTEST
Reserved
2
Data register to be selected
Boundary scan register
Boundary scan register
1
Bypass register
Reserved
TMP19A44
LSB
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