tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 272

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DMA Controller (DMAC)
Bit
31
24
23
22
21
20
19
18
17
16
15
14
13
12
11
Mnemonic
AbIEn
NIEn
SReq
PosE
ExR
Big
Lev
Str
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Channel start
(Reserved)
Normal completion
interrupt enable
Abnormal
completion interrupt
enable
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Big-endian
(Reserved)
(Reserved)
External request
mode
Positive edge
Level mode
Snoop request
Field name
Starts channel operation. If this bit is set to 1, the channel goes into a standby
mode and starts to transfer data in response to a transfer request.
Only a write of 1 is valid to the Str bit and a write of 0 is ignored. A read always
returns a 0.
1: Starts channel operation
Normal Completion Interrupt Enable (initial value: 1)
1: Normal completion interrupt enable
0: Normal completion interrupt disable
Abnormal Completion Interrupt Enable (initial value: 1)
1: Abnormal completion interrupt enable
0: Abnormal completion interrupt disable
This is a reserved bit. Although it’s initial value is "1," always set this bit to "0."
Big Endian (initial value: 1)
1: A channel operates by big-endian
0: A channel operates by little-endian
External Request Mode (initial value: 0)
Selects a transfer request mode. (only for 0ch and 4ch)
1: External transfer request (interrupt request or external DREQn request)
0: Internal transfer request (software initiated)
The effective level of the transfer request signal INTDREQn or DREQn is
specified. This function is valid only if the transfer request is an external transfer
request (if the ExR bit is 1). If it is an internal transfer request (if the ExR bit is
0), the PosE value is ignored. Because the INTDREQn and DREQn signals are
active at "L" level, make sure that this PosE bit is set to "0."
1: Setting prohibited
0: The falling edge of the INTDREQn or DREQn signal or the "L" level is
Specifies which is used to recognize the external transfer request, signal level or
signal change. This setting is valid only if a transfer request is the external
transfer request (if the ExR bit is 1). If the internal transfer request is specified as
a transfer request (if the ExR bit is 0), the value of the Lev bit is ignored. Because
the INTDREQn signal is active at "L" level, make sure that you set the Lev bit to
"1." The state of active DREQn is determined by the Lev bit setting.
1: Level mode
0: Edge mode
The use of the snoop function is specified by asserting the bus control request
mode. If the snoop function is used, the snoop function of the TX19A/ H1
processor core is enabled and the DMAC can use the data bus of the TX19A /H1
processor core. If the snoop function is not used, the snoop function of the
TX19A/ H1 processor core does not work.
1: Use snoop function (SREQ)
0: Do not use snoop function (GREQ)
Start (initial value:–)
This is a reserved bit. Always set this bit to "0."
This is a reserved bit. Always set this bit to "0."
This is a reserved bit. Always set this bit to "0."
This is a reserved bit. Always set this bit to "0."
This is a reserved bit. Always set this bit to "0."
This is a reserved bit. Always set this bit to "0."
Positive Edge (initial value: 0)
Level Mode (initial value: 0)
Snoop Request (initial value: 0)
TMP19A44 (rev1.3) 10-9
effective. The DACKn is active at "L" level.
The level of the DREQn signal is recognized as a data transfer request.
(The "L" level is recognized if the PosE bit is 0.
A change in the DREQn signal is recognized as a data transfer request.
(A falling edge is recognized if the PosE bit is 0.)
Description
TMP19A44
2010-04-01