tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 66

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.3.2 General Exception Handling
(Note 2) An error virtual address is stored when an address error exception occurs.
(Note 1) Cause<BD> bit of the CP0 register is set to
6.3.2.1 Flowchart
General exception factor
Returning to preceding
CPU Handles interrupt
CPU branches off to
-“1”: when an exception is generated by an instruction in a jump/ branch slot.
-“0”: other than the above.
ErrorEPC normally stores PC of the instruction causes an exception. It stores PC of a
jump/ branch instruction when an exception is generated by an instruction in a jump/
branch slot.
Execute exception
exception handler
The following shows how a hardware interrupt is handled.
The CPU detects
handler program
is generated.
Processing
program
interrupt
indicates hardware handling.
TMP19A44(rev1.3) 6-16
The interrupt factor is generated.
The CPU detects the interrupt.
The CPU handles the interrupt.
The following bits in the CP0 register are automatically set.
The CPU branches off to the exception vector address
(0xBFC0_0380).
Program for the exception handler.
Configure to return to the preceding program from the exception
handler.
CP0:
CP0:
CP0:
CP0:
CP0:
CP0:
indicates software handling.
Status<EXL>
EPC
Cause<BD>
Cause<ExcCode>
BadVAddr
SSCR<PSS>
Details
←
←
←
←
←
←
“1”
“PC of exception”(Note
1)
“1/0”(Note 1)
Exception factor code
Error address (Note 2)
Register
(when
occurs)
TMP19A44
2010-04-01
set
exception
number