tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 52

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.1 Overview
Exceptions/Interrupts
6.1.1.1
6.1.1.2
6.1.1 Exceptions and Interrupts
・Prioritization according to interrupt level
・Shadow register
・DMAC activation
section 6.2 or later for details.
Interrupts are classified into general interrupt and debug interrupt.
to the genera purpose register (GPR).
referred to as “interrupt”.
interrupt” or “hardware interrupt” respectively.
This section roughly describes features, types and process flow of exceptions and interrupts. Please refer to the
Exceptions and interrupts request the CPU to stop the ongoing processing and execute other processing.
General exception is caused by an abnormal condition or an instruction to generate an exception.
Debug exception is used when debugging.
Interrupts are classified into two types. One is maskable hardware interrupt of which factor is
The features of the mast able interrupts are as follows:
The 19A44 can handle multiple interrupts according to the seven programmable interrupt priority levels. By
setting a mask level, an interrupt of which level is lower than the specified can be masked.
A register bank ”Shadow Register Set” enables high-speed response to an interrupt without storing the contents
An interrupt can be used as DMAC activator. It requires settings in the interrupt controller.
Hereinafter general interrupts and debug interrupts are referred to as “exception”, maskable interrupts are
If maskable interrupt factors are divided into software-generated or hardware-generated, we call them “software
hardware-generated (i.e. interrupt request signal from external pin or peripheral IP). Another is Maskable
software interrupt that is caused by software. They are generically named as maskable interrupts.
Interrupts features
Exceptions features
TMP19A44(rev1.3) 6-2
TMP19A44
2010-04-01