tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 87

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.5.2.5
(1) Factors of hardware interrupt
(2) Condition of not Generating Interrupt
Detection by CPU
1) Status<ERL> or Status<EXL> bit is set
2) In debug mode
3) The CPU is stalled
following conditions. The factor is suspended until the condition is changed as interrupt-acceptable.
or a general exception other than reset / NMI occurs. After an exception or an interrupt is generated,
hardware interrupts are prohibited.
program enables hardware interrupts. These bits automatically return to “0” when returning from exception
handler by ERET instruction.
instruction, a hardware interrupt is ignored.
A hardware interrupt factor is recognized by the CPU when the following three settings are configured.
1) Status<IM> (interrupt mask) is “111”.
2) Status<IE> (interrupt enable bit) is “1”.
3) Interrupt level notified from INTC is more than “1”.
Even if the three settings shown above are completed, a hardware interrupt cannot be generated under the
Status<ERL> bit is set to “1” when reset or NMI occurs. Status<EXL> bit is set to “1” when an interrupt
Both Status<ERL> and Status<EXL> bits are rewritable. Writing these bits to “0”using exception handler
In debug mode, which is defined as duration from debug exception generation to returning by DRET
When the CPU is stalled for any reason, a hardware interrupt is not generated.
TMP19A44(rev1.3) 6-37
TMP19A44
2010-04-01