tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 247

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

External Bus Interface
2 waits automatically inserted
2 waits automatically inserted + 2N (N=1)
3 waits automatically inserted + 2N (N=1)
2 waits automatically inserted + 2N (N=2)
Fig. 8.13 shows the read operation timing when 0 wait, waits automatically inserted, and waits
automatically inserted + external waits are inserted in the multiplexed bus mode.
0 wait
fsys
A[23:16]
AD[15:0]
A[23:16]
AD[15:0]
A[23:16]
AD[15:0]
A[23:16]
AD[15:0]
A[23:16]
AD[15:0]
/WAIT
/WAIT
/WAIT
/WAIT
/WAIT
ALE
/RD
ALE
/RD
ALE
/RD
ALE
/RD
ALE
/RD
--- External wait sampling point
External wait sampling points take place before a cycle of waits automatically
inserted is finished and before a 2N_wait cycle is finished as shown above.
The same applies to combinations of other numbers of waits.
Fig. 8.13 Read Operation Timing Diagram
Lower-order address
Lower-order address
Lower-order address
Lower-order address
Lower-order address
TMP19A44 (rev1.3) 8-19
tsys
2 waits automatically
2 waits automatically
2 waits automatically
Higher-order address
Higher-order address
Higher-order address
Higher-order address
Higher-order address
3 waits automatically
inserted
inserted
inserted
Data
inserted
Data
2N_WAIT
2N_WAIT
2N_WAIT
TMP19A44
Data
Data
2010-04-01
Data