tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 403

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Transmit Buffer
Serial Channel (HSIO)
The send buffer (HSC0BUF) is in a dual structure. The double buffering function may be enabled or
disabled by setting the double buffer control bit <WBUF> in serial mode control register 2
(HC0MOD2). If double buffering is enabled, data written to send buffer 2 (SCOBUF) is moved to send
buffer 1 (shift register).
If the transmit FIFO has been disabled (HSCOFCNF <CNFG> = 0 or 1 and <FDPX1:0> = 01/11), the
HINTTX interrupt is generated at the same time and the send buffer empty flag <TBEMP> of
HC0MOD2 is set to "1." This flag indicates that send buffer 2 is now empty and that the next transmit
data can be written. When the next data is written to send buffer 2, the <TBEMP> flag is cleared to "0."
If the transmit FIFO has been enabled (HSCNFCNF <CNFG> = 1 and <FDPX1:0> = 10/11), any data
in the transmit FIFO is moved to the send buffer 2 and <TBEMP> flag is immediately cleared to "0."
The CPU writes data to send buffer 2 or to the transmit FIFO.
If the transmit FIFO is disabled in the I/O interface HSCLK input mode and if no data is set in send
buffer 2 before the next frame clock input, which occurs upon completion of data transmission from
send buffer 1, an under-run error occurs and a serial control register (HC0CR) <PERR> parity/under-
run flag is set.
If the transmit FIFO is enabled in the I/O interface HSCLK input mode, when data transmission from
send buffer 1 is completed, the send buffer 2 data is moved to send buffer 1 and any data in transmit
FIFO is moved to send buffer 2 at the same time.
If the transmit FIFO is disabled in the I/O interface HSCLK output mode, when data in send buffer 2 is
moved to send buffer 1 and the data transmission is completed, the HSCLK output stops. So, no under-
run errors can be generated.
If the transmit FIFO is enabled in the I/O interface HSCLK output mode, the HSCLK output stops upon
completion of data transmission from send buffer 1 if there is no valid data in the transmit FIFO.
Note)
If double buffering is disabled, the CPU writes data only to send buffer 1 and the transmit interrupt
HINTTX is generated upon completion of data transmission.
If handshaking with the other side is necessary, set the double buffer control bit <WBUF> to "0"
(disable) to disable send buffer 2; any setting for the transmit FIFO should not be performed.
In the I/O interface HSCLK output mode, the HC0CR <PEER> flag is
insignificant. In this case, the operation is undefined. Therefore, to switch from
the HSCLK output mode to another mode, HC0CR must be read in advance to
initialize the flag.
TMP19A44(rev1.3) 15-13
TMP19A44
2010-04-01