tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 4

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8. External Bus Interface
9. The Chip Selector and Wait Controller
10. DMA Controller (DMAC)
11. 16-bit Timer/Event Counters (TMRBs)
8.1 Address and Data Pins
8.2 Data Format
8.3 External Bus Operations (Separate Bus Mode)
8.4 External Bus Operations (Multiplexed Bus Mode)
8.5 Bus Arbitration
9.1 Specifying Address Spaces
9.2 The Chip Selector and Wait Controller
10.1 Features
10.2 Configuration
10.3 Registers
10.4 Functions
10.5 Timing Diagrams
10.6 Case of Data Transfer
11.1 Block Diagram of Each Channel
11.2 Register Description
11.3 Description of Operations for Each Circuit
9.1.1 Base and Mask Address Setting Registers
9.1.2 How to Define Start Addresses and Address Spaces
10.2.1 Internal Connections of the TMP19A44
10.2.2 DMAC Internal Blocks
10.2.3 Snoop Function
10.3.1 DMA Control Register (DCR)
10.3.2 Channel Control Registers (CCRn)
10.3.3 Request Select Register (RSR)
10.3.4 Channel Status Registers (CSRn)
10.3.5 Source Address Registers (SARn)
10.3.6 Destination Address Register (DARn)
10.3.7 Byte Count Registers (BCRn)
10.3.8 DMA Transfer Control Register (DTCRn)
10.3.9 Data Holding Register (DHR)
10.4.1 Overview
10.4.2 Transfer Request
10.4.3 Address Mode
10.4.4 Channel Operation
10.4.5 Order of Priority of Channels
10.5.1 Dual Address Mode
10.5.2 DREQn-Initiated Transfer Mode
11.2.1 TMRB registers
11.3.1 Prescaler
11.3.2 Up-counter (UC0) and Time Up-counter Registers (TB0UC)
11.3.3 Timer Registers (TB0RG0, TB0RG1)
11.3.4 Capture Registers (TB0CP0, TB0CP1)
11.3.5 Capture
TMP19A44(rev1.3)-iii
TMP19A44
8-1
8-2
8-3
8-9
8-17
8-24
9-1
9-1
9-1
9-4
9-7
10-1
10-1
10-2
10-2
10-3
10-3
10-4
10-6
10-8
10-11
10-12
10-14
10-15
10-16
10-17
10-18
10-19
10-19
10-22
10-25
10-26
10-27
10-28
10-28
10-30
10-34
11-1
11-3
11-4
11-4
11-6
11-6
11-9
11-9
11-10
11-10