tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 486

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Watchdog Timer
18.4 Operation Description
The watchdog timer generates the INTWDT interrupt after a lapse of the detection time specified by the
WDMOD <WDTP2, 0> register. Before generating the INTWD interrupt, the binary counter for the watchdog
timer must be cleared to "0" using software (instruction). If the CPU malfunctions (runs away) due to noise or
other disturbances and cannot execute the instruction to clear the binary counter, the binary counter overflows
and the INTWD interrupt is generated. The CPU is able to recognize the occurrence of a malfunction (runaway)
by identifying the INTWD interrupt and to restore the faulty condition to normal by using a malfunction
(runaway) countermeasure program. Additionally, it is possible to resolve the problem of a malfunction
(runaway) of the CPU by connecting the watchdog timer out pin to reset pins of peripheral devices.
The watchdog timer begins operation immediately after a reset is cleared.
In STOP mode, the watchdog timer is reset and in an idle state. When the bus is open ( BUSAK = "L"), it
continues counting. In IDLE mode, its operation depends on the WDMOD <I2WDT> setting. Before putting it
in IDLE mode, WDMOD <I2WDT> must be set to an appropriate setting, as required.
Examples:
Note:
If the watchdog timer is operated when the high-frequency oscillator is idle, the
system reset operation initiated by the watchdog timer becomes erratic due to the
unstable oscillation of the high-frequency oscillator. Therefore, do not operate the
watchdog timer when the high-frequency oscillator is idle.
To clear the binary counter
To set the detection time of the watchdog timer to 2
To disable the watchdog timer
(Runaway Detection Timer)
WDCR
WDMOD
WDMOD
WDCR
← 0 1 0 0 1 1 1 0
← 1 0 1
← 0 − − − − − − −
← 1 0 1 1 0 0 0 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
− − − − −
TMP19A44(rev0.3) 18-5
Writes the clear code (4EH)
Clears WDTE to "0"
Writes the disable code (B1H)
18
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SYS
TMP19A44
2010-04-01