tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 287

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DMA Controller (DMAC)
DREQn
A[31:1]
DACKn
− Edge mode
In the edge mode, the DMAC detects the falling edge of the DREQn signal. If it detects the
falling edge of the DREQn signal upon the rising of the internal system clock (the case in
which the "L" level is detected upon the rising of the system clock although it was not
detected upon the rising of the previous system clock) when a channel is in a standby mode, it
judges that there is a transfer request, goes into transfer mode, and starts a transfer operation.
To detect the falling edge of the DREQn signal, the PosE bit (bit 13) of the CCRn register
must be set to "0," and the Lev bit (bit 12) must also be set to "0." The DACKn signal is active
at the "L" level.
If the falling edge of the DREQn signal is detected after the DACKn signal is asserted, the
next data is transferred without a pause.
If there is no falling edge of the DREQn signal after the DACKn signal is asserted, the
DMAC judges that there is no transfer request, and starts a transfer operation for other
channels or goes into a standby mode after releasing bus control authority.
The unit of a transfer request is specified in the TrSiz field (<bit3:2>) of the CCRn register.
Fig. 10.14 Transfer Request Timing (Edge Mode)
TMP19A44 (rev1.3) 10-24
Transfer data
Transfer data
TMP19A44
2010-04-01