tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 229

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8.
External Bus Interface
External Bus Interface
The TMP19A44 has a built-in external bus interface function to connect to external memory, I/Os, etc. This
interface consists of an external bus interface circuit (EBIF), a chip selector (CS) and a wait controller.
The chip selector and wait controller designate mapping addresses in a 4-block address space and also control
wait states and data bus widths (8- or 16-bit) in these and other external address spaces.
The external bus interface circuit (EBIF) controls the timing of external buses based on the chip selector and
wait controller settings. The EBIF also controls the dynamic bus sizing and the bus arbitration with the external
bus master.
External bus mode
Selectable address, data separator bus mode and multiplex mode
Wait function
This function can be enabled for each block.
Data bus width
Either an 8- or 16-bit width can be set for each block.
Recovery cycle (read/write)
If an external bus cycle is in progress, a dummy cycle of up to 4 clocks can be inserted and this dummy
cycle can be specified for each block.
Recovery cycle (chip selector)
When an external bus is selected, a dummy cycle of up to 8 clocks can be inserted and this dummy cycle
can be specified for each block.
Bus arbitration function
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A wait of up to 15 clocks can be automatically inserted.
A wait can be inserted via the WAIT / RDY pin.
TMP19A44 (rev1.3) 8-1
TMP19A44
2010-04-01