tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 286

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DMA Controller (DMAC)
A transfer request made by the interrupt controller (INTC)
A transfer request made by the interrupt controller is cleared using the DACKn signal. This
DACKn signal is asserted only if a bus cycle for single transfer or the number of bytes (value
set in the BCRn register) transferred at continuous transfer becomes "0." Therefore, at the
single transfer, the amount of data specified by TrSiz is transferred only once because
INTDREQn is cleared upon completion of one data transfer from one transfer request. On the
other hand, at the continuous transfer, it can be transferred successively in response to a
transfer request because INTDREQn is not cleared until the number of bytes transferred
(value set in the BCRn register) becomes "0."
Note that if the DMAC acknowledges an interrupt set in INTDREQn and if this interrupt is
cleared by the INTC before DMA transfer begins, there is a possibility that DMA transfer
might be executed once after the interrupt is cleared, depending on the timing.
A transfer request made by an external device
External pins (DREQ0 and DREQ4) are internally wired to allow them to function as pins of
the port 5 and the port A. These pins can be selected by setting the function control register
PFFC to an appropriate setting.
In the edge mode, the DREQn signal must be negated and then asserted for each transfer
request to create an effective edge. In the level mode, however, successive transfer requests
can be recognized by maintaining an effective level. At the continuous transfer, only the "L"
level mode can be used. At the single transfer, only the falling edge mode can be used.
− Level mode
In the level mode, the DMAC detects the "L" level of the DREQn signal upon the rising of the
internal system clock. If it detects the "L" level of the DREQn signal when a channel is in a
standby mode, it goes into transfer mode and starts to transfer data. To use the DREQn signal
at an active level, the PosE bit (bit 13) of the CCRn register must be set to "0." The DACKn
signal is active at the "L" level, as in the case of the DREQn signal.
If an external circuit asserts the DREQn signal, the DREQn signal must be maintained at the
"L" level until the DACKn signal is asserted. If the DREQn signal is negated before the
DACKn signal is asserted, a transfer request may not be recognized.
If the DREQn signal is not at the "L" level, the DMAC judges that there is no transfer request,
and starts a transfer operation for other channels or releases bus control authority and goes
into a standby mode.
The unit of a transfer request is specified in the TrSiz field (<bit3:2>) of the CCRn register.
DREQn
A[31:1]
DACKn
Fig. 10.13 Transfer Request Timing (Level Mode)
TMP19A44 (rev1.3) 10-23
Transfer data
TMP19A44
2010-04-01