tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 64

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
(Note) Cause<BD> bit of the CP0 register is set to
6.2.2.4
6.2.2.5
6.2.2.3
6.2.2.2
Returning to preceding
To distinguish which one is generated, refer to the Status<NMI> bit of the CP0 register. Indicating “0”
means reset exception is generated. Indicating “1” means non-maskable interrupt is generated. This bit is not
changed by other exceptions/ interrupts.
NMIFLG register in the CG register.
exception right after power-on, a value stored in the register is undefined since the PC value is undefined.
-“1”: when an exception is generated by an instruction in a jump/ branch slot.
-“0”: other than the above.
ErrorEPC normally stores PC of the instruction causes an exception. It stores PC of a
jump/ branch instruction when an exception is generated by an instruction in a jump/
branch slot.
Execute exception
A reset exception and non-maskable interrupt are branch off to the same reset exception vector address.
A non-maskable interrupt has multiple interrupt factors. To distinguish which factor is used, refer to the
If “1” is set to the Status<EXL> bit, interrupts are prohibited.
“1” is set to the Status<EXL> bit due to exception handling of the CPU when a reset exception/
non-maskable interrupt occurs. This bit is automatically cleared to “0” when returning from an exception
handler by executing the ERET instruction.
To execute an interrupt while handling an exception, set “0”.
The ErrorEPC register in the CP0 register stores PC of the instruction causes an exception. As for a reset
See “6.1.3.6 Returning from Exceptions/ interrupts”.
handler program
Processing
How to Distinguish Reset Exception and Non-maskable Interrupt
Status<EXL> Bit of the CP0 Register
PC Stored in the ErrorEPC
Return from Exception Handler
program
TMP19A44(rev1.3) 6-14
Program for the exception handler.
Configure to return to the preceding program from the exception
handler.
Details
TMP19A44
2010-04-01