tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 273

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(Note 1) The CCRn register setting must be completed before the DMAC is put into a standby mode.
(Note 2) In executing continuous data transfer, a value set in DPS becomes invalid.
(Note 3) Set the mode first and then set the <Str> bit.
DMA Controller (DMAC)
10
9
8 : 7
6
5 : 4
3 : 2
1 : 0
Bit
Mnemonic
RelEn
SIO
SAC
DIO
DAC
TrSiz
DPS
Bus control release
request enable
Transfer type
selection
Source address count
(Reserved)
Destination address
count
Transfer unit
Device port size
Field name
Fig. 10.4 Channel Control Registers (CCRn) (2 of 2)
Release Request Enable (initial value: 0)
Acknowledgment of the bus control release request made by the TX19A/ H1
processor core is specified. This function is valid only if GREQ is generated. If
SREQ is generated, the TX19A/ H1 processor core cannot make a bus control
release request and, therefore, this function cannot be used.
1: The bus control release request is acknowledged if the DMAC has control of
0: The bus control release request is not acknowledged.
Transfer type selection: (initial value: 0)
1 Single transfer
0: Continuous transfer (Data is transferred successively until BCRx becomes "0")
Specifies the manner of change in a source address.
1x: Address fixed
01: Address decrease
00: Address increase
This is a reserved bit. Always set this bit to “0”.
Destination Address Count (initial value: 00)
Specifies the manner of change in a destination address.
1x: Address fixed
01: Address decrease
00: Address increase
Specifies the amount of data to be transferred in response to one transfer request.
11: 8 bits (1 byte)
10: 16 bits (2 bytes)
0x: 32 bits (4 bytes)
*This needs to be set to the same size as that of the device port size (DPS).
Specifies the bus width of an I/O device designated as a source or destination
device.
11: 8 bits (1 byte)
10: 16 bits (2 bytes)
0x: 32 bits (4 bytes)
*This needs to be set to the same size as that of the transfer unit (TrSiz).
Source Address Count (initial value: 00)
Transfer Size (initial value: 00)
Device Port Size (initial value: 00)
TMP19A44 (rev1.3) 10-10
the bus. If the TX19A/ H1 processor core issues a bus control release request,
the DMAC relinquishes control of the bus to the TX19A/ H1 processor core
during a pause in bus operation.
Description
TMP19A44
2010-04-01