tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 400

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Channel (HSIO)
Receive buffer 2
Receive buffer 1
Receive interrupt
I/O interface mode with HSCLK input:
The following example describes the case a 32-byte data stream is received:
HSC0FCNF <4:0> = 10101: Automatically allows continued reception after reaching the fill level.
SC0RFC <4:0> = 11111: Sets the interrupt to be generated at fill level 32.
SC0RFC <7:6> = 10: Clears receive FIFO and sets the condition of interrupt generation
In this condition, 32-byte data reception can be initiated along with the input clock by setting the
half duplex transmission mode and writing "1" to the RXE bit. When the 4-byte data reception is
completed, the receive FIFO interrupt will be generated.
Note that preparation for the next data reception can be managed in this setting, i.e., the next 32-
byte data can be received before data is fully read from the FIFO.
RX FIFO
RBFLL
RXE
Fig. 15-4 Receive FIFO Operation
1 byte
TMP19A44(rev1.3) 15-10
The number of bytes to be used in the receive FIFO is the maximum
allowable number.
1 byte
2 byte
1 byte
2 byte
3 byte
1 byte
2 byte
3 byte
4 byte
3 byte
1 byte
2 byte
TMP19A44
4 byte
2010-04-01
4 byte
3 byte
2 byte
1 byte
32byte