tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 463

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(Note 1) If AD conversion is executed with the match triggers <ADHTG> and <HADHTG> of a 16-bit
(Note 2) Do not make a top-priority AD conversion setting and a normal AD conversion setting
(Note 3) The external trigger cannot be used for H/W activation of AD conversion when it is used for
Analog/Digital Converter
ADAMOD4
(0xFF00_4D14)
ADMOD3
(0xFF00 _4D10)
ADMOD5
(0xFF00 _4D18)
timer set to "1" by using a source for triggering H/W, A/D conversion can be activated at
specified intervals by performing three steps shown below when the timer is idle:
simultaneously.
H/W activation of top priority AD conversion.
Select a source for triggering HW: <ADHS>, <HADHS>
Enable H/W activation of AD conversion: <ADHTG>, <HADHTG>
Start the timer.
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
Function
Function
Function
<REGSA2, 1, 0>
Write "0."
Write "0."
HW source for
activating
top-priority
A/D
conversion
0: External
1: TB9RG0
HADHSA
TRG
R/W
R/W
7
7
0
0
7
Fig. 17.4 Registers related to the A/D Converter
0
1XXX
0000
0001
0010
0011
"0" is read.
"0" is read.
HW for
activating
top-priority
A/D
conversion
0: Disable
1: Enable
HADHTGA
6
R
6
R
0
0
6
0
TMP19A44(rev1.3) 17-4
A/D Mode Control Register 3
A/D Mode Control Register 5
A/D Mode Control Register 4
Make AD monitor
function interrupt
setting
0: Smaller than
1: Larger than
Make AD monitor
function interrupt
setting
0: Smaller than
1: Larger than
R/W
comparison
register
comparison
register
comparison
register
comparison
register
HW source for
activating
normal A/D
conversion
0: External
1: TB1RG0
ADOBICA
ADOBICA
ADHSA
TRG
5
5
0
0
5
0
AD conversion result storage register
HW for
activating
normal A/D
conversion
0: Disable
1: Enable
ADHTGA
BIT for selecting the AD conversion result storage register
that is to be compared with the comparison register if the AD
monitor function is enabled
BIT for selecting the AD conversion result storage register
that is to be compared with the comparison register if the AD
monitor function is enabled
REGSA3
REGSA3
to be compared
4
0
ADAREGSP
4
4
0
0
ADAREG0
ADAREG1
ADAREG2
ADAREG3
“0” is read.
REGSA2
REGSA2
3
3
3
0
0
R/W
R/W
R
0
REGSA1
REGSA1
2
2
2
0
0
TMP19A44
Overwriting 10 with 01 allows
ADC to be software reset.
ADRSTA1 ADRSTA0
REGSA0
REGSA0
W
1
1
1
0
0
−
AD monitor
function
0: Disable
1: Enable
AD monitor
function
0: Disable
1: Enable
2010-04-01
ADOBSVA
ADOBSVA
W
0
0
0
0
0
−