tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 297

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DMA Controller (DMAC)
10.6 Case of Data Transfer
The settings described below relate to a case in which serial data received (SCnBUF) is transferred to the
internal RAM by DMA transfer.
DMA (ch.0) is used to transfer data. The DMA0 is activated by a receive interrupt generated by SIO1.
<DMA setting>
<Serial channel setting>
<SIO ch.1 setting>
<DMA0 setting>
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IMC09
INTCLR
SC1MOD0
SC1CR
BR1CR
DCR
IMC17
INTCLR
IMC17
DTCR0
SAR0
DAR0
BCR0
CCR0
Channel used: 0
Source address: SC1BUF
Destination: (Physical address) 0xFFFF_A000
Number of bytes transferred: 256 bytes
Data length 8 bits: UART
Serial channel: 1 ch
Transfer rate: 9600 bps
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31
15
1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
0 1 0 1 1 x 1 1 x 0 0 0 1 1 1 1
x111, x000
0x098
0x29
0x00
0x1F
0x8000_0000
x000, x000
0x17C
x000, x100
0x0000_0000
0xFF00_4C44
0xFFFF_9800
0x0000_00FF
0x80C0_5B0F
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TMP19A44 (rev1.3) 10-34
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/* assigned to DMC0 activation factor * /
/* IVR [8:0], INTRX1 interrupt factor * /
/* UART mode, 8-bit length, baud rate generator * /
/*φT4, N=15*/
/* DMA reset * /
/* disable interrupt * /
/* IVR [8:0] value * /
/* level = 4 (any given value) */
/* DACM = 000 * /
/* SACM = 000 * /
/* physical address of SC1BUF */
/* physical address of destination to which data is transferred */
/* 256 (number of bytes transferred) /
/* DMA ch.0 setting */
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TMP19A44
2010-04-01