tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 71

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.4.2.2
(Note) Cause<BD> bit of the CP0 register is set to
Interrupt Factor Indication
Returning to preceding
simultaneously. In this case, a hardware interrupt has a priority if a shadow register is available.
Cause<IP>[1:0] indicates “1”, it is the software interrupt factor. If any of the Cause<IP>[4:2] indicates “1”,
it is the hardware interrupt factor. Detecting both interrupts simultaneously enables both factors.
ErrorEPC normally stores PC of the instruction causes an exception. It stores PC of a
jump/ branch instruction when an exception is generated by an instruction in a jump/
branch slot.
not recognized even if the Cause<IP> is set to “1” when corresponding Status<IM> is “0”.
-“1”: when an exception is generated by an instruction in a jump/ branch slot.
-“0”: other than the above.
Execute exception
A software interrupt uses the same exception handler as a hardware interrupt. These interrupts may occur
The Cause<IP>[4:0] and Status<IM>[4:0] of the CP0 register indicate an interrupt factor. If any of the
The Status<IM>[4:0] and Cause<IP>[4:0] can mask a factor. They need to be used together. A factor is
The Cause<IP>[4:2] bits do not indicate an individual interrupt factor. It indicates interrupt level of a
handler program
hardware interrupt. See “6.5 Hardware Interrupt” for details of hardware interrupt.
Processing
program
TMP19A44(rev1.3) 6-21
Program for the exception handler.
Clear the interrupt factor if needed.
Read INTC IVR register.
Configure to return to the preceding program from the exception
handler.
Details
TMP19A44
2010-04-01