tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 109

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
IMCGD
(Note 1)
(Note 2)
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
Refer to EMSTxx bit to know the active condition which is used for clearing
standby.
Please specify the bit for the edge first and then specify the bit for the
<INTxEN>. Setting them simultaneously is prohibited.
“0” is read. Active state setting of
“0” is read. Active state setting of
“0” is read. Active state setting of
“0” is read. Active state setting of
15
23
31
R
R
R
R
7
0
0
0
0
Set it as shown below.
Set it as shown below.
Set it as shown below.
Set it as shown below.
standby clear request.
standby clear request.
standby clear request.
standby clear request.
001: “H” level
010: Falling edge
011: Rising edge
011: Rising edge
EMCGC
EMCGD
EMCGE
EMCGF
14
22
30
6
2
2
2
2
0
0
0
0
TMP19A44(rev1.3) 6-59
EMCGC
EMCGD
EMCGE
EMCGF
R/W
R/W
R/W
R/W
13
21
29
5
1
1
1
1
1
1
1
1
KWUP
INTRTC
PHCNT0
PHCNT1
EMCGC
EMCGD
EMCGE
EMCGF
12
20
28
4
0
0
0
0
0
0
0
0
read.
Undefined value is
Undefined value is
read.
Undefined value is
read.
Undefined value is
read.
11
19
27
3
-
-
-
-
R
R
R
R
10
18
26
2
-
-
-
-
TMP19A44
“0” is read. KWUP clear
“0” is read. INTRTC
“0” is read. PHCNT0
“0” is read. PHCNT1
17
25
1
R
9
R
R
R
0
0
0
0
2010-04-01
input
0: Disable
1: Enable
clear input
0: Disable
1: Enable
clear input
0: Disable
1: Enable
clear input
0: Disable
1: Enable
PHCNT0
PHCNT1
KWUPE
INTRTCE
R/W
R/W
EN
R/W
EN
R/W
16
24
N
0
8
N
0
0
0
0