tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 441

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Bus Interface (SBI)
16.6
16.6.1
16.6.2
First, program SBICR1<ACK, SCK2:0> by writing "0" to bits 7 to 5 and bit 3 in SBICR1.
Next, program I2CAR by specifying a slave address at <SA6:0> and an address recognition mode at
<ALS>. (<ALS> must be set to"0" when using the addressing format.)
Next, program SBICR2 to initially configure the SBI in the slave receiver mode by writing "0" to
<MST, TRX, BB> , "1" to <PIN> , "10" to <SBIM1:0> and "0" to bits 1 and 0.
Settings in main routine
Example of INTS0 interrupt routine
Data Transfer Procedure in the I
Master mode
In the master mode, the following steps are required to generate the start condition and a slave
address.
First, ensure that the bus is free (<BB> = "0"). Then, write "1" to SBICR1 <ACK> to select the
acknowledgment mode. Write to SBIDBR a slave address and a direction bit to be transmitted.
When <BB> = "0," writing "1111" to SBICR2 <MST, TRX, BB, PIN> generates the start condition
on the bus. Following the start condition, the SBI generates nine clocks from the SCL pin. The
SBI outputs the slave address and the direction bit specified at SBIDBR with the first eight clocks,
and releases the SDA line in the ninth clock to receive an acknowledgment signal from the slave
device.
The INTS0 interrupt request is generated on the falling of the ninth clock, and <PIN> is cleared to
"0." In the master mode, the SBI holds the SCL line at the "L" level while <PIN> is "0." <TRX>
changes its value according to the transmitted direction bit at generation of the INTS0 interrupt
request, provided that an acknowledgment signal has been returned from the slave device.
INTCLR ← 0xbc
Processing
End of interrupt
SBICR1
I2CAR
SBICR2
(Note) X: Don't care
Reg.
Reg.
if Reg.
Then
SBICR1
SBIDR1
SBICR2
Device Initialization
Generating the Start Condition and a Slave Address
≠ 0x00
← 0 0 0 X 0 X X X
← X X X X X X X X
← 0 0 0 1 1 0 0 0
← SBISR
← Reg. e 0x20
← X X X 1 0 X X X
← X X X X X X X X
← 1 1 1 1 1 0 0 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
TMP19A44 (rev1.3) 16-17
Clears the interrupt request.
Specifies ACK and SCL clock.
Specifies a slave address and an address recognition mode.
Configures the SBI as a slave receiver.
Ensures that the bus is free.
Selects the acknowledgement mode.
Specifies the desired slave address and direction.
Generates the start condition.
2
C Bus Mode
TMP19A44
2010-04-01