tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 55

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.1.3.1
external interrupt pin and peripheral I/O)
(1) Exception request
“Abnormal conditions during instructions”, “Instructions to generate exceptions” and “Debug register setting”.
(2) Interrupt request
interrupt)
An exception or an interrupt request is generated by various factors (i. e. instruction executed by the CPU,
An exception request is mainly caused by an abnormal condition detected during executing an instruction.
The following list categorized the types of the exceptions into four groups: “Requests not from the CPU”,
An interrupt request is caused by software (software interrupt), an external pin or a peripheral IP (hardware
To make interrupt request, setting of the CP0 register, CG and interrupt controller are required. Details are
described in “6.5 Hardware interrupt”.
Generation of exception/ interrupt request
●Requests not from the CPU
●Abnormal conditions during instructions
fetch/ load/ store）
fetch/ load/ store）
●Instructions to generate exceptions
●Debug register setting
Reset exception
Non-maskable interrupt (NMI）
Address error exception (instruction
Bus error exception (instruction
Co-processor unusable exception
Integer overflow exception
Reserved instruction exception
System call exception
Debug breakpoint exception
Breakpoint exception
Trap exception
Single step exception
Table 6.1 Exception types and factors
TMP19A44(rev1.3) 6-5
Reset signal
WDT
External NMI pin
Instruction fetch from the address undesignated.
Reading operand in the address undesignated.
Instruction fetch from the unused area
Reading operand in the unused area
Executing co-processor instruction without setting
the CU bit of the status register in the co-processor.
Overflow of ADD, ADDI or SUB instruction result
Executing undefined instruction code
Executing SYSCALL instruction
Executing SDBBP instruction
Executing BREAK instruction
Executing TGE, TGEU, TLT, TLTU, TEQ TNE,
TGEI, TGEIU, TLTI, TLTIU, TEQI and TNEI
instructions.
Setting SSt bit in the Debug register
TMP19A44
2010-04-01