tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 480

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Analog/Digital Converter
17.3.5
17.3.6
17.3.7
By interrupting ongoing normal A/D conversion, top-priority A/D conversion can be performed. Top-
priority A/D conversion can be software activated by setting ADnMOD2<HPADCE> to "1" or it can be
activated using the HW resource by setting ADnMOD4<7:6> to an appropriate setting. If top-priority
A/D conversion has been activated during normal A/D conversion, ongoing normal A/D conversion is
interrupted, and single conversion is performed for a channel designated by ADnMOD2<3:0>. The
result of single conversion is stored in ADnREGSP, and the top-priority A/D conversion interrupt is
generated. After top-priority A/D conversion is completed, normal A/D conversion is resumed; the
status of normal A/D conversion immediately before being interrupted is maintained. Top-priority A/D
conversion activated while top-priority A/D conversion is under way is ignored.
For example, if channel repeat conversion is activated for channels ANC0 through ANC7 and if
<HPADCE> is set to "1" during ANC3 conversion, AN3 conversion is suspended, and conversion is
performed for a channel designated by <HPADC3:0>. After the result of conversion is stored in
ADCREGSP, channel repeat conversion is resumed, starting from ANC3.
If ADnMOD3<ADOBSV> is set to "1," the A/D monitor function is enabled. If the value of the
conversion result storage register specified by REGS<3:0> becomes larger or smaller ("larger" or
"smaller" to be designated by ADOBIC) than the value of a comparison register, the A/D monitor
function interrupt is generated. This comparison operation is performed each time a result is stored in a
corresponding conversion result storage register, and the interrupt is generated if the conditions are met.
Because storage registers assigned to perform the A/D monitor function are usually not read by software,
overrun flag <OVRn> is always set and the conversion result storage flag <ADnRRF> is also set. To
use the A/D monitor function, therefore, a flag of a corresponding conversion result storage register
must not be used.
Two values can be specified in each unit at a time for the comparison.
A/D conversion results are stored in upper and lower A/D conversion result registers for normal A/D
conversion (ADAREG0 through ADARG3, ADBREG0 through ADBRG3, ADCREG0 through
ADCRG7).
In fixed channel repeat conversion mode, A/D conversion results are sequentially stored in ADnREG0
through ADnREG3 and ADnREG7. If <ITM1:0> is so set as to generate the interrupt each time one
A/D conversion is completed, conversion results are stored only in ADnREG0. If <ITM1:0> is so set as
to generate the interrupt each time four A/D conversions are completed, conversion results are
sequentially stored in ADnREG0 through ADnREG3.
Table 17.1 shows analog input channels and related A/D conversion result registers.
High-priority Conversion Mode
A/D Monitor Function
Storing and Reading A/D Conversion Results
TMP19A44(rev1.3) 17-21
TMP19A44
2010-04-01