tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 404

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Transmit FIFO Buffer
Transmit FIFO Operation
Serial Channel (HSIO)
In addition to the double buffer function already described, data may be stored using the transmit FIFO
buffer. By setting <CNFG> of the HSC0FCNF register and <FDPX1:0> of the HSC0MOD1 register,
the 32-byte send buffer can be enabled. In the UART mode or I/O interface mode, up to 32bytes of data
may be stored.
If data is to be transmitted with a parity bit in the UART mode, parity check must be performed on the
receive side each time a data frame is received.
note. Please execute clear the transmit FIFO after the forwarding mode setting
I/O interface mode with HSCLK output (normal mode):
The following example describes the case a 4-byte data stream is transmitted:
HSC0FCNF <4:0> = 01011: Inhibits continued transmission after reaching the fill level.
HSC0TFC <5:0> = 00000: Sets the interrupt to be generated at fill level 0.
HSC0TFC <7:6> = 01: Clears transmit FIFO and sets the condition of interrupt generation
In this condition, data transmission can be initiated by setting the transfer mode to half duplex,
writing 4 bytes of data to the transmit FIFO, and setting the <TXE> bit to "1." When the last
transmit data is moved to the send buffer, the transmit FIFO interrupt is generated. When
transmission of the last data is completed, the clock is stopped and the transmission sequence is
terminated.
and the permission of FIFO of SIO when you use the transmit FIFO buffer.
Send buffer 1
Send buffer 2
TX FIFO
TBEMP
INTTX0
TXE
Fig. 15-8 Transmit FIFO Operation
TMP19A44(rev1.3) 15-14
Data 1
Data 6
Data 5
Data 4
Data 3
Data 2
Data 2
Data 6
Data 5
Data 4
Data 3
Data 3
Data 6
Data 5
Data 4
Data 4
Data 6
Data 5
Data 6
Data 5
TMP19A44
2010-04-01