tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 371

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.2.19 software reset
14.2.20 Signal Generation Timing
Serial Channel (SIO)
Software reset is HSC0MOD2 <SWRST1:0>“10” → “01”
SC0MOD0 ＜ RXE ＞、 SC0MOD1<TXE> ， SC0MOD2 ＜ TBEMP ＞ , ＜ RBFLL ＞ , ＜ TXRUN ＞、
SC0CR ＜ OERR ＞、＜ PERR ＞、＜ FERR ＞ and internal circuit is initialized.
Other states are maintained.
UART Mode:
Receive Side
Transmit Side
I/O interface mode:
Receive Side
Transmit Side
Interrupt generation
timing
Framing error timing
Parity error generation
timing
Overrun error generation
timing
Interrupt generation
timing
Interrupt generation
timing
Interrupt generation
timing
(WBUF = 0)
Interrupt generation
timing
(WBUF = 1)
Overrun error
generation timing
Interrupt generation
timing
(WBUF = 0)
Interrupt generation
timing
(WBUF = 1)
(<WBUF> = 0)
(<WBUF> = 1)
Mode
Mode
SCLK output
mode
SCLK input mode Immediately after the rising or falling edge of the last SCLK (for
SCLK output
mode
SCLK input mode Immediately after the rising edge or falling edge of the last SCLK
SCLK input mode Immediately after the rising or falling edge of the last SCLK (for
SCLK output
mode
SCLK input mode Immediately after the rising or falling edge of the last SCLK (for
SCLK output
mode
SCLK input mode Immediately after the rising or falling edge of the last SCLK (for
TMP19A44(rev1.3) 14-19
Around the center
of the 1st stop bit
Around the center
of the stop bit
Around the center
of the stop bit
Just before the stop
bit is sent
Immediately after
data is moved to
send buffer 1 (just
before start bit
transmission)
9-bit
9-bit
⎯
Immediately after the rising edge of the last SCLK
rising or falling edge mode, respectively)
Immediately after the rising edge of the last SCLK (just after data
transfer to receive buffer 2) or just after receive buffer 2 is read
depending on the rising or falling edge triggering mode,
respectively (right after data is moved to receive buffer 2)
rising or falling edge mode, respectively)
Immediately after the rising edge of the last SCLK
rising or falling edge mode, respectively)
Immediately after the rising edge of the last SCLK or just after
data is moved to send buffer 1
the rising or falling edge mode, respectively) or just after data is
moved to send buffer 1
Around the center of the
1st stop bit
Around the center of the
stop bit
Around the center of the
last (parity) bit
Around the center of the
stop bit
Just before the stop bit is
sent
Immediately after data is
moved to send buffer 1
(just before start bit
transmission)
8-bit with parity
8-bit with parity
Just before the stop bit is sent
Immediately after data is moved to
send buffer 1 (just before start bit
transmission)
Around the center of the 1st stop bit
Around the center of the stop bit
Around the center of the last (parity)
bit
Around the center of the stop bit
8-bit, 7-bit, and 7-bit with parity
8-bit, 7-bit, and 7-bit with parity
TMP19A44
2010-04-01