tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 435

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Bus Interface (SBI)
16.5
16.5.1
16.5.2
16.5.3
Setting SBICR1<ACK> to "1" selects the acknowledge mode. When operating as a master, the SBI
adds one clock for acknowledgment signals. As a transmitter, the SBI releases the SDA pin during this
clock cycle to receive acknowledgment signals from the receiver. As a receiver, the SBI pulls the SDA
pin to the "L" level during this clock cycle and generates acknowledgment signals.
Setting <ACK> to "0" selects the non-acknowledgment mode. When operating as a master, the SBI
does not generate clock for acknowledgement signals.
SBICR1 <BC2:0> specifies the number of bits of the next data to be transmitted or received.
Under the start condition, <BC2:0> is set to "000," causing a slave address and the direction bit to be
transferred in a packet of eight bits. At other times, <BC2:0> keeps a previously programmed value.
The highest speeds in the standard and high-speed modes are specified to 100KHz
and 400KHz respectively in the communications standards. Note that the internal SCL
clock frequency is determined by the fsys used and the calculation formula shown
above.
Control Registers in the I
Clock source
SBICR1 <SCK2:0> specifies the maximum frequency of the serial clock to be output from the
SCL pin in the master mode.
Setting the Acknowledgement Mode
Setting the Number of Bits per Transfer
Serial Clock
t
t
fscl = 1/(t
LOW
HIGH
= 2
=
= 2
n-1
Low
n-1
2
fsys/2
n
/(fsys/2) + 58/(fsys/2)
/(fsys/2) + 12/(fsys/2)
+ 70
+ t
HIGH
t
HIGH
)
TMP19A44 (rev1.3) 16-11
Fig. 16.3 Clock Source
t
LOW
2
C Bus Mode
SBI0CR1 <SCK2:0>
000
001
010
011
100
101
110
1/fscl
10
11
n
5
6
7
8
9
TMP19A44
2010-04-01