tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 618

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Flash Memory Operation
5) Automatic chip erase
6) Automatic block erase (one block at a time)
7) Automatic programming of protection bits
Note:
The automatic chip erase operation starts when the sixth bus write cycle of the command cycle is
completed.
This condition can be checked by monitoring FLCS [0] <FlashBusy> (See Table 24.10). While no
automatic verify operation is performed internally to the device, be sure to read the data to confirm
that data has been correctly erased. Any new command sequence is not accepted while it is in an
automatic chip erase operation. If it is desired to stop operation, use the hardware reset function. If
the operation is forced to stop, it is necessary to perform the automatic chip erase operation again
because the data erasing operation has not been normally terminated.
Also, any protected blocks cannot be erased. If all the protected blocks are protected, the automatic
chip erase operation will not be performed and it returns to the read mode after completing the
sixth bus read cycle of the command sequence. When an automatic chip erase operation is
normally terminated, it automatically returns to the read mode. If an automatic chip erase operation
has failed, the flash memory is locked in the mode and will not return to the read mode.
For returning to the read mode, it is necessary to use the reset command or hardware reset to reset
the flash memory or the device. In this case, the failed block cannot be detected. It is recommended
not to use the device anymore or to identify the failed block by using the block erase function for
not to use the identified block anymore.
The automatic block erase operation starts when the sixth bus write cycle of the command cycle is
completed.
This status of the automatic block erase operation can be checked by monitoring FLCS [0]
<FlashBusy> (See Table 24.10). While no automatic verify operation is performed internally to the
device, be sure to read the data to confirm that data has been correctly erased. Any new command
sequence is not accepted while it is in an automatic block erase operation. If it is desired to stop
operation, use the hardware reset function. In this case, it is necessary to perform the automatic
block erase operation again because the data erasing operation has not been normally terminated.
Also, any protected blocks cannot be erased. If an automatic block erase operation has failed, the
flash memory is locked in the mode and will not return to the read mode. In this case, use the reset
command or hardware reset to reset the flash memory or the device.
This device is implemented with four protection bits. The protection bits can be individually set in
the automatic programming. The applicable protection bit is specified in the seventh bus write
cycle. By automatically programming the protection bits, write and/or erase functions can be
inhibited (for protection) individually for each area. The protection status of each area can be
checked by the FLCS <PROTECT 3:0> register to be described later. This status of the automatic
programming operation to set protection bits can be checked by monitoring FLCS <FlashBusy>
(See Table 24.10). Any new command sequence is not accepted while automatic programming is in
progress to program the protection bits. If it is desired to stop the programming operation, use the
hardware reset function. In this case, it is necessary to perform the programming operation again
Software reset becomes ineffective in bus write cycles on and after the fourth
bus write cycle of the automatic page programming command.
TMP19A44 (rev1.3)24-33
TMP19A44
2010-04-01