M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 832

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

830
2nd edition
Edition
Modification of Figure 12-8 One-Shot Select 1-Buffer Mode Operation Timing (When
ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits = 10, ADA0M2.ADA0BS bit = 0,
ADA0S.ADA0S2 to ADA0S.ADA0S0 bits = 001): V850E/IA4
Modification of Figure 12-9 One-Shot Select 4-Buffer Mode Operation Timing (When
ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits = 10, ADA0M2.ADA0BS bit = 1,
ADA0S.ADA0S2 to ADA0S.ADA0S0 bits = 011): V850E/IA4
Modification of Figure 12-10 One-Shot Scan Mode Operation Timing (When
ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits = 11, ADA0S.ADA0S2 to
ADA0S.ADA0S0 bits = 011): V850E/IA4
Modification of description in Figures 12-11 to 12-16 in 12.5 Operation in Software
Trigger Mode
Modification of description in 12.6 Operation in Timer Trigger Modes 0 and 1
Modification of description in 12.7 Operation in External Trigger Mode
Addition of 12.8 Internal Equivalent Circuit
Addition of description to 12.9.1 Stopping conversion operation
Modification of description in 12.9.2 (1) When 0 < trigger occurrence interval < total
number of A/D conversion clocks
Addition of Caution 3 in 13.4.1 Basic operation
Addition of description to Figures 13-4 to 13-7
Addition of 13.5 Internal Equivalent Circuit
Modification of Figure 14-2 Block Diagram of UARTAn
Modification of description and deletion of Caution in 14.4 (1) UARTAn control register 0
(UAnCTL0)
Addition of Caution in 14.4 (5) UARTAn status register (UAnSTR)
Modification of description in 14.6.3 Continuous transmission procedure
Addition of Caution in 14.6.5 Reception errors
Modification of description in Figure 14-8 Noise Filter Circuit
Addition of Figure 14-9 Timing of RXDAn Signal Judged as Noise
Addition of Caution in 14.7 (2) UARTAn control register 1 (UAnCTL1)
Addition of Caution in 14.7 (3) UARTAn control register 2 (UAnCTL2)
Modification of description in Table 14-3 Baud Rate Generator Setting Data
Addition of 14.8 Cautions
Modification of Figure 15-2 Block Diagram of CSIBn
Addition of Remark in 15.3 (2) CSIBn transmit data register (CBnTX)
Modification of description in 15.4 (1) CSIBn control register 0 (CBnCTL0)
Addition of Caution and modification of description in 15.4 (2) CSIBn control register 1
(CBnCTL1)
Modification of description in 15.5 Operation
Modification of description in 15.6 (1) SCKBn pin
Modification of description in 15.7 Operation Flow
Modification of Caution description in 16.3.6 DMA trigger factor registers 0 to 3 (DTFR0
to DTFR3)
Addition of description in 16.8 (2) During DMA transfer (period from the generation of
DMA transfer request to completion of DMA transfer)
APPENDIX D REVISION HISTORY
User’s Manual U16543EJ4V0UD
Description
CHAPTER 12
A/D CONVERTERS
0 AND 1
CHAPTER 13
A/D CONVERTER 2
CHAPTER 14
ASYNCHRONOUS
SERIAL INTERFACE
A (UARTA)
CHAPTER 15
CLOCKED SERIAL
INTERFACE B
(CSIB)
CHAPTER 16
DMA FUNCTIONS
(DMA
CONTROLLER)
Applied to:
(3/6)