M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 206

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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204
TPkIOC2
(d) TMPk I/O control register 2 (TPkIOC2)
(e) TMPn counter read buffer register (TPnCNT)
(f) TMPn capture/compare register 0 (TPnCCR0)
(g) TMPn capture/compare register 1 (TPnCCR1)
Note Enable setting of the TPkEES1 and TPkEES0 bits only when timer output (TOPk1) is used.
By reading the TPnCNT register, the count value of the 16-bit counter can be read.
If the TPnCCR0 register is set to D
Interval = (D
The TPnCCR1 register is not used in the interval timer mode. However, the set value of the TPnCCR1
register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches
the value of the CCR1 buffer register, the TOPm1 pin output is inverted and a compare match interrupt
request signal (INTTPnCC1) is generated.
By setting this register to the same value as the value set in the TPmCCR0 register, a PWM waveform
with a duty factor of 50% can be output from the TOPm1 pin.
When the TPnCCR1 register is not used, it is recommended to set its value to FFFFH. Also mask the
register by the interrupt mask flag (TPnCCIC1.TPnCCMK1).
Remarks 1. TMPk I/O control register 1 (TPkIOC1) and TMPn option register 0 (TPnOPT0) are not
0
In this case, set the TPkCCR0 and TPkCCR1 registers to the same value.
Figure 6-11. Register Setting for Interval Timer Mode Operation (2/2)
2. V850E/IA3: n = 0 to 3, m = 0, 2, k = 0, 2, a = 0, 1
0
0
+ 1) × Count clock cycle
used in the interval timer mode.
V850E/IA4: n = 0 to 3, m = 0, 2, 3, k = 0, 2, a = 0, 1
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
0
0
User’s Manual U16543EJ4V0UD
0
, the interval is as follows.
TPkEES1
0/1
Note
TPkEES0 TPkETS1 TPkETS0
0/1
Note
0
0
Selection of valid edge of external
event count input (TIPk0 pin)