M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 569

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(4) 4-buffer parallel mode
Figure 13-7. Example of Operation Timing in 4-Buffer Parallel Mode (with 8-Bit Resolution, f
Remarks 1. Data:
Notes 1. The ANI26 and ANI27 pins are only available in the V850E/IA4.
A/D conversion of the analog input pin (ANI2n)
in parallel, with a time difference. The conversion results are continuously stored in four A/D2 conversion
result registers n (ADA2CRn) corresponding to the ANI2n pin
The conversion results of one of the ANI20 to ANI23 pins are stored in the ADA2CR0 to ADA2CR3 registers,
and those of one of the ANI24 to ANI27 pins
Figure 13-2).
A/D conversion is performed with a time difference that is 1/4 of the conversion time set by the ADA2CTL1
register.
After the four the A/D conversion, the A/D2 conversion end interrupt request signal (INTAD2) is generated
when the conversion results are stored in the four ADA2CRn registers. After end of A/D conversion, it is
repeated again with the same ANI2n pin, unless the ADA2CTL0.ADA2CE bit is cleared to 0 (conversion
stopped).
It is not required to set (1) the ADA2CTL0.ADA2CE bit to restart A/D conversion
A/D conversion can be stopped by clearing the ADA2CE bit to 0.
A/D2 conversion
result register n
2. In 4-buffer parallel mode, unless the ADA2CTL0.ADA2CE bit is cleared to 0, A/D conversion is not
2. n = 0 to 7
3. f
INTAD2 interrupt
stopped. Therefore, the contents of the ADA2CRn register must be read before A/D conversion
ends, or the register is overwritten (n = 0 to 7).
DF counter
DF counter: Digital filter
The A/D conversion results of one of the ANI20 to ANI23 pins are stored in the ADA2CR0 to
ADA2CR3 registers.
The A/D conversion results of one of the ANI24 to ANI27 pins are stored in the ADA2CR4 to
ADA2CR7 registers.
The above chart shows an example of the operation timing when one of the ANI20 to ANI23
pins is selected.
XX
ADA2CE bit
ADA2CR0
ADA2CR1
ADA2CR2
ADA2CR3
: Peripheral clock
Conversion data
Data 0
224 s + 6 clocks
Data 1
μ
CHAPTER 13 A/D CONVERTER 2
Data 2
Data 3
User’s Manual U16543EJ4V0UD
Data 0
Data 4
Data 5
Data 1
Note 1
Note 1
Data 2
Data 6
Data 7
specified by the ADA2CTL2 register is performed four times
128 s
Data 3
are stored in the ADA2CR4 to ADA2CR7 registers (see
Data 4
μ
Data 8
Data 9
Data 5
Data 10
Data 6
Note 1
Data 11
Data 7
(n = 0 to 7).
Data 12
Data 8
Data 13
Data 9
Data 10
Data 14
Data 15
Data 11
Note 2
Data 12
Data 16
Data 13
Data 17
.
Data 18
Data 14
Data 19
Data 15
Data 16
Data 20
XX
Data 17
Data 21
Data 22
= 64 MHz)
Data 18
Data 23
Data 19
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