M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 200

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
198
Remarks 1. D
(b) Batch write
In this mode, data is transferred all at once from the TPmCCR0 and TPmCCR1 registers to the CCR0 and
CCR1 buffer registers during timer operation. This data is transferred upon a match between the value of
the CCR0 buffer register and the value of the 16-bit counter. Transfer is enabled by writing to the
TPmCCR1 register.
Whether to enable or disable the next transfer timing is controlled by writing or not writing to the TPmCCR1
register.
In order for the setting value when the TPmCCR0 and TPmCCR1 registers are rewritten to become the 16-
bit counter comparison value (in other words, in order for this value to be transferred to the CCR0 and
CCR1 buffer registers), it is necessary to rewrite the TPmCCR0 register and then write to the TPmCCR1
register before the 16-bit counter value and the CCR0 buffer register value match. Therefore, the values of
the TPmCCR0 and TPmCCR1 registers are transferred to the CCR0 and CCR1 buffer registers upon a
match between the count value of the 16-bit counter and the value of the CCR0 buffer register. Thus even
when wishing only to rewrite the value of the TPmCCR0 register, also write the same value (same as
preset value of the TPmCCR1 register) to the TPmCCR1 register.
2. The above timing chart illustrates an example of the operation in the interval timer mode.
3. n = 0 to 3
CCR0 buffer register
CCR1 buffer register
D
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
01
11
, D
, D
16-bit counter
02
12
: Setting values of TPnCCR0 register
: Setting values of TPnCCR1 register
FFFFH
0000H
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
TPnCE bit = 1
0000H
0000H
Figure 6-6. Timing of Anytime Write
D
User’s Manual U16543EJ4V0UD
11
D
D
01
11
D
D
11
D
01
11
D
01
D
01
D
12
D
D
D
02
12
12
D
D
D
02
02
12

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