M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 581

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(6) UARTAn receive data register (UAnRX)
(7) UARTAn transmit data register (UAnTX)
The UAnRX register is an 8-bit buffer register that stores parallel data converted by the UARTAn receive shift
register.
The data stored in the UARTAn receive shift register is transferred to the UAnRX register upon end of reception
of 1 byte of data. A reception end interrupt request signal (INTUAnR) is generated at this timing.
During LSB-first reception when the data length has been specified as 7 bits, the receive data is transferred to
bits 6 to 0 of the UAnRX register and the MSB always becomes 0. During MSB-first reception, the receive data
is transferred to bits 7 to 1 of the UAnRX register and the LSB always becomes 0.
When an overrun error occurs (UAnSTR.UAnOVE bit = 1), the receive data at this time is not transferred to the
UAnRX register and is discarded.
This register is read-only, in 8-bit units.
In addition to reset, the UAnRX register can be set to FFH by clearing the UAnCTL0.UAnPWR bit to 0.
The UAnTX register is an 8-bit register used to set transmit data.
Transmission starts when transmit data is written to the UAnTX register in the transmission enabled status
(UAnCTL0.UAnTXE bit = 1). Upon end of the transfer of the data of the UAnTX register to the UARTAn
transmit shift register, the transmission enable interrupt request signal (INTUAnT) is generated.
This register can be read or written in 8-bit units.
Reset sets this register to FFH.
(n = 0, 1)
(n = 0, 1)
UAnRX
UAnTX
After reset: FFH
After reset: FFH
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
7
7
R
R/W
6
6
Address: UA0RX FFFFFA06H, UA1RX FFFFFA16H
Address: UA0TX FFFFFA07H, UA1TX FFFFFA17H
User’s Manual U16543EJ4V0UD
5
5
4
4
3
3
2
2
1
1
0
0
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