M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 542

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.9 Notes on Operation
12.9.1 Stopping conversion operation
the conversion results are not stored in A/Dn conversion result register m (ADAnCRm).
generated in all modes.
12.9.2 Timer/external trigger interval
than the total number of conversion clocks specified by the ADAnM1.ADAnFR1 and ADAnM1.ADAnFR0 bits (see
Table 12-2 Number of Conversion Clocks).
540
Caution For operation when using the operational amplifier for input level amplification, refer to 12.3 (3)
When the ADAnM0.ADAnCE bit is cleared to 0 during a conversion operation, the conversion operation stops and
The ADAnCE bit is not cleared to 0 even after the A/Dn conversion end interrupt request signal (INTADn) has been
Remark
Make sure that the occurrence interval of the trigger in timer trigger mode 0, 1, or external trigger mode is longer
(1) When 0 < trigger occurrence interval < total number of A/D conversion clocks
(2) When trigger occurrence interval ≥ total number of A/D conversion clocks
When the timer/external trigger is input during a conversion operation, the conversion operation is aborted and
the conversion starts according to the last timer/external trigger input.
When conversion operations are aborted, the conversion results from the conversion operation immediately
before are not stored in the ADAnCRm register. Note, therefore, that the generation of the INTADn signal and
storing of the result in the ADAnCRm register are not guaranteed.
Remark
The INTADn signal is generated, and the value at the end of conversion is correctly stored in the ADAnCRm
register. Design so that the trigger occurrence interval is equal or greater than the total number of A/D
conversion clocks.
Remark
A/D converter n channel specification register (ADAnS) (n = 0, 1).
For the relationship between the analog input pins and A/D conversion result registers, see
Table 12-4.
n = 0, 1
m = 0 to 3
n = 0, 1
m = 0 to 3
n = 0, 1
m = 0 to 3
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U16543EJ4V0UD