M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 580

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

578
(n = 0, 1)
UAnSTR
After reset: 00H
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
UAnOVE
The UAnTSF bit is always 1 when performing continuous transmission. When
initializing the transmission unit, check that the UAnTSF bit = 0 before performing
initialization. The transmit data is not guaranteed when initialization is performed
while the UAnTSF bit = 1.
• The operation of the UAnPE bit is controlled by the settings of the
• The UAnPE bit can be read and written, but it can only be cleared by writing 0 to it,
• Only the first bit of the receive data stop bits is checked, regardless of the value
• The UAnFE bit can be both read and written, but it can only be cleared by
• When an overrun error occurs, the data is discarded without the next receive data
• The UAnOVE bit can be both read and written, but it can only be cleared by writing
UAnTSF
UAnTSF
UAnPE
UAnFE
the value is retained.
is retained.
UAnCTL0.UAnPS1 and UAnCTL0.UAnPS0 bits.
and it cannot be set by writing 1 to it. When 1 is written to this bit, the value is
retained.
of the UAnCTL0.UAnSL bit.
writing 0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit,
being written to the UAnRX register.
0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit, the value
<7>
0
1
0
1
0
1
0
1
• When the UAnPWR bit = 0 or the UAnTXE bit = 0 has been set.
• When, following transfer end, there was no next data transfer from
Write to UAnTX register
• When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set.
• When 0 has been written
When parity of data and parity bit do not match during reception.
• When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set.
• When 0 has been written
When no stop bit is detected during reception
• When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set.
• When 0 has been written
When receive data has been set to the UAnRX register and the next
receive operation is ended before that receive data has been read.
R/W
UAnTX register
6
0
Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H
User’s Manual U16543EJ4V0UD
5
0
4
0
Transfer status flag
Overrun error flag
Framing error flag
Parity error flag
3
0
UAnPE
<2>
UAnFE
<1>
UAnOVE
<0>