M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 483

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4.6 A/D conversion start trigger output function
INTTPnCC0, INTTPnCC1) to generate the A/D conversion start trigger signal (TQTADTn0, TQTADTn1) of A/D
converters 0 and 1.
TQnOPT3.TQnAT13 bits.
ORed and output. Therefore, two or more trigger sources can be specified at the same time.
culled interrupt signals.
(TQnOPT1.TQnICE, TQnOPT1.TQnIOE bits), the A/D conversion start trigger is not output.
trigger signal depending on the status of the count-up/count-down of the 16-bit counter, if so set by the TQnAT02,
TQnAT03, TQnAT12, and TQnAT13 bits.
The V850E/IA3 and V850E/IA4 have a function to select four trigger sources (INTTQnOV, INTTQnCC0,
The trigger sources are specified by the TQnOPT2.TQnAT00 to TQnOPT2.TQnAT03 and TQnOPT3.TQnAT10 to
• TQnAT00, TQnAT10 bits = 1:
• TQnAT01, TQnAT11 bits = 1:
• TQnAT02, TQnAT12 bits = 1:
• TQnAT03, TQnAT13 bits = 1:
The A/D conversion start trigger signals selected by the TQnAT00 to TQnAT03 and TQnAT10 to TQnAT13 bits are
The INTTQnOV and INTTQnCC0 signals selected by the TQnAT00, TQnAT01, TQnAT10, and TQnAT11 bits are
Therefore, these signals are output after the interrupts have been culled and, unless interrupt output is enabled
The trigger sources (INTTPnCC0 and INTTPnCC1) from TMPn have a function to mask the A/D conversion start
• TQnATM02, TQnATM12 bits:
• TQnATM03, TQnATM13 bits:
• TQnATM02, TQnATM12 bits = 0
• TQnATM02, TQnATM12 bits = 1
• TQnATM03, TQnATM13 bits = 0
The A/D conversion start trigger signal is output when the 16-bit counter counts up (TQnOPT0.TQnCUF bit =
0), and the A/D conversion start trigger signal is not output when the 16-bit counter counts down
(TQnOPT0.TQnCUF bit = 1).
The A/D conversion start trigger signal is output when the 16-bit counter counts down (TQnOPT0.TQnCUF
bit = 1), and the A/D conversion start trigger signal is not output when the 16-bit counter counts up
(TQnOPT0.TQnCUF bit = 0).
The A/D conversion start trigger signal is output when the 16-bit counter counts up (TQnOPT0.TQnCUF bit =
0), and the A/D conversion start trigger signal is not output when the 16-bit counter counts down
(TQnOPT0.TQnCUF bit = 1).
Correspond to the TQnAT02 and TQnAT12 bits and control INTTPnCC0 (match interrupt signal) of TMPn.
Correspond to the TQnAT03 and TQnAT13 bits and control INTTPnCC1 (match interrupt signal) of TMPn.
A/D conversion start trigger signal generated when INTTQnOV (counter underflow) occurs.
A/D conversion start trigger signal generated when INTTQnCC0 (cycle match) occurs.
A/D conversion start trigger signal generated when INTTPnCC0 (match of TPnCCR0 register of TMPn
during tuning operation) occurs.
A/D conversion start trigger signal generated when INTTPnCC1 (match of TPnCCR1 register of TMPn
during tuning operation) occurs.
CHAPTER 10 MOTOR CONTROL FUNCTION
User’s Manual U16543EJ4V0UD
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