M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 238

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOPm1 pin.
After the one-shot pulse is output, the 16-bit counter is cleared to 0000H, stops counting, and waits for a trigger.
When the trigger is generated again, the 16-bit counter starts counting from 0000H. If a trigger is generated again
while the one-shot pulse is being output, it is ignored.
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTPmCC1
is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register.
is used as the trigger.
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When the TPmCE bit is set to 1, 16-bit timer/event counter P waits for a trigger. When the trigger is generated, the
The output delay period and active level width of the one-shot pulse can be calculated as follows.
The compare match interrupt request signal INTTPmCC0 is generated when the 16-bit counter counts after its
The valid edge of an external trigger input (TIPk0 pin) or setting the software trigger (TPmCTL1.TPmEST bit) to 1
Remark
External trigger input
INTTPmCC0 signal
INTTPmCC1 signal
TPmCCR0 register
TPmCCR1 register
TOPm1 pin output
Output delay period = (Set value of TPmCCR1 register) × Count clock cycle
Active level width = (Set value of TPmCCR0 register − Set value of TPmCCR1 register + 1) × Count clock cycle
TOP00 pin output
(only when using
(TIPk0 pin input)
software trigger)
16-bit counter
TPmCE bit
V850E/IA3: m = 0, 2, k = 0, 2
V850E/IA4: m = 0, 2, 3, k = 0, 2
FFFFH
0000H
Figure 6-28. Basic Timing in One-Shot Pulse Output Mode
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Delay
(D
D
1
1
)
Active
level width
(D
D
User’s Manual U16543EJ4V0UD
0
0
− D
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
D
D
0
0
1
0
− D
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
0
0
− D
1
+ 1)