M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 479

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4.5 TMPn tuning operation for A/D conversion start trigger signal output
as a slave. The conversion start trigger signal of A/D converters 0 and 1 can be set as the A/D conversion start trigger
source by the INTTPnCC0 and INTTPnCC1 signals of TMPn and the INTTQnOV and INTTQnCC0 signals of TMQn.
This section explains the tuning operation of TMPn and TMQn in the 6-phase PWM output mode.
In the 6-phase PWM output mode, the tuning operation is performed with TMQn serving as the master and TMPn
Remark
(1) Tuning operation starting procedure
The TMPn and TMQn registers should be set using the following procedure to perform the tuning operation.
(a) Setting of TMPn register (stop the operations of TMQn and TMPn (by clearing the TQnCTL0.TQnCE
(b) Setting of TMQn register
(c) Setting of TMQOPn (TMQn option) register
(d) Setting of alternate function
bit and TPnCTL0.TPnCE bit to 0))
• Set the TPnCTL1 register to 85H (set the tuning operation slave mode and free-running timer mode).
• Clear the TP0IOC0 to TP0IOC2 registers to 00H (the I/O function for TMP0 is not used)
• Clear the TP0OPT0 register to 00H (select the compare register).
• Set an appropriate value to the TPnCCR0 and TPnCCR1 registers (set the default value for comparison
Note Valid only for TMP0 (not available for TMP1).
• Set the TQnCTL1 register to 07H (set the master mode and 6-phase PWM output mode).
• Set an appropriate value to the TQnIOC0 register (set the output mode of TOQnT1 to TOQnT3).
• Clear the TQ0IOC1 and TQ0IOC2 registers to 00H (TIQ00 to TIQ03, the EVTQ0, and TRGQ0 pins of
• Clear the TQnOPT0 register to 00H (select the compare register).
• Set an appropriate value to the TQnCCR0 to TQnCCR3 registers (set the default value for comparison
• Set the TQnCTL0 register to 0xH (clear the TQnCE bit to 0 and set the operating clock of TMQn).
Note Valid only for TMQ0 (not available for TMQ1).
• Set an appropriate value to the TQnOPT1 and TQnOPT2 registers.
• Set an appropriate value to the TQnIOC3 register (set TOQnB1 to TOQnB3 in the output mode).
• Set an appropriate value to the TQnDTC register (set the default value for comparison for starting the
• Select the alternate function of the port by setting the port to the port control mode.
V850E/IA3: n = 0
V850E/IA4: n = 0, 1
for starting the operation).
However, clear the TQnOL0 bit to 0 and set the TQnOE0 bit to 1 (enable positive phase output). Unless
this setting is made, the crest interrupt (INTTQnCC0) and valley interrupt (INTTQnOV) do not occur.
Consequently, the conversion start trigger signal of A/D converters 0 and 1 is not correctly generated.
TMQ0 are not used)
for starting the operation).
The operating clock of TMQn set by the TQnCTL0 register is also supplied to TMPn, and the count
operation is performed at the same timing. The operating clock of TMPn set by the TPnCTL0 register is
ignored.
operation).
Note
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CHAPTER 10 MOTOR CONTROL FUNCTION
User’s Manual U16543EJ4V0UD
Note
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