M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 309

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
<R>
(g) TMQn capture/compare registers 1 to 3 (TQnCCR1 to TQnCCR3)
The TQnCCR1 to TQnCCR3 registers are not used in the interval timer mode. However, the set values
of the TQnCCR1 to TQnCCR3 registers are transferred to the CCR1 to CCR3 buffer registers. When the
count value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers, the TOQ01 to
TOQ03 pin outputs are inverted and the compare match interrupt request signals (INTTQnCC1 to
INTTQnCC3) are generated.
When the TQnCCR1 to TQnCCR3 registers are not used, it is recommended to set their values to
FFFFH.
TQnCCIC3.TQnCCMK3).
Remarks 1. TMQ0 I/O control register 1 (TQ0IOC1) and TMQn option register 0 (TQnOPT0) are not
2. n = 0, 1
Figure 7-9. Register Setting for Interval Timer Mode Operation (3/3)
Also mask the registers by the interrupt mask flags (TQnCCIC1.TQnCCMK1 to
used in the interval timer mode.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
User’s Manual U16543EJ4V0UD
307

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