M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 567

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A/D2 conversion result
register n (ADA2CRn)
(2) 1-buffer parallel mode
Figure 13-5. Example of Operation Timing in 1-Buffer Parallel Mode (with 8-Bit Resolution, f
Remarks 1. D:
INTAD2 interrupt
Notes 1. The ANI26 and ANI27 pins are only available in the V850E/IA4.
A/D conversion of the analog input pin (ANI2n)
in parallel, with a time difference. The conversion results are continuously stored in A/D2 conversion result
register n (ADA2CRn) corresponding to the ANI2n pin
The ANI2n pin
A/D conversion is performed with a time difference that is 1/4 of the conversion time set by the ADA2CTL1
register.
After conversion, the A/D2 conversion end interrupt request signal (INTAD2) is generated each time the
conversion result is stored in the ADA2CRn register corresponding to the ANI2n pin
time). After the end of the first conversion, conversion is repeated unless the ADA2CTL0.ADA2CE bit is
cleared to 0 (conversion stopped).
It is not required to set (1) the ADA2CTL0.ADA2CE bit to restart A/D conversion
A/D conversion can be stopped by clearing the ADA2CE bit to 0.
DF counter
ADA2CE bit
2. In 1-buffer parallel mode, unless the ADA2CTL0.ADA2CE bit is cleared to 0, A/D conversion is not
2. n = 0 to 7
3. f
stopped. Therefore, the contents of the ADA2CRn register must be read before A/D conversion
ends, or the register is overwritten (n = 0 to 7).
DF counter: Digital filter
When the ANI2n pin is selected, the result of conversion is stored in the ADA2CRn register.
XX
: Peripheral clock
Note 1
128 s + 6 clocks
and the ADA2CRn register correspond one to one (see Table 13-2).
μ
D0
Conversion data
D1
D2
D0
D3
CHAPTER 13 A/D CONVERTER 2
32 s
D1
μ
D4
User’s Manual U16543EJ4V0UD
D2 D3
D5
D6
Note 1
D4 D5
D7
specified by the ADA2CTL2 register is performed four times
D8
Note 1
D6
D9
(n = 0 to 7).
D7 D8
D10
D11
D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19
D12
D13
D14
D15
Note 2
.
D16
Note 1
D17
(each 1/4 conversion
D18
XX
D19
= 64 MHz)
D20
D21
D22
D23
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